1. Field of the Invention
The present invention relates to a method for forming a mask pattern for use in making electrodes and circuits and ion implanting in manufacturing semiconductor devices. Also the present invention relates to a compound semiconductor device and to a method of the production thereof, particularly to a device in which a Schottky gate type field effect transistor or metal semiconductor field effect transistor (referred to as MESFET hereinafter) is used.
2. Description of the prior art
When a gate electrode, circuit or a region for implanting impurities are formed in an integrated circuit (IC), a mask pattern is previously made. In a process for manufacturing a MESFET of a recess gate type for example, there is formed an opening in a resist by a photo-lithographic method and metallic substance are deposited through the opening, whereby a gate electrode is formed (see page 80 in "Super high speed Compound Semiconductor Device" published by Baifukan). In this manner, according to the known technology, the gate electrodes of approximately 1.0 .mu.m wide can be made.
However, in the prior art mentioned above, it is difficult to form fine circuit patterns finer than 1.0 .mu.m in width due to the resolution of the optical system in the photo-lithography and to the developing precision of the photo resist layer. In order to realize the fine circuit patterns, the pattern manufacturing apparatus becomes complicated and expensive.
Besides the above, generally, a gallium arsenide (GaAs) field-effect transistor (referred to as "GaAs-MESFET" hereinafter) has a good property especially in a super-high frequency wave range, which is used in a small signal amplifier and oscillator. Also, it has been well known that a GaAs-MESFET has a very good property as a basic component of a super-high speed integrated circuit. There are various advantages such that, in a field-effect transistor (referred to as "FET" hereinafter), there can be obtained a high impedance compared to a bipolar transistor, and that the delay time due to the storage effect of the minority carriers is small because the FET is the majority carrier device, and that the relation between the input voltage and the output current generally represents a square characteristic and there occurs little noise, and that it can be integrated with high density because the component has a simple structure.
FIG. 1 shows the structure of a GaAs-MESFET generally used in the prior art. Ionized impurities such as Si.sup.+ are implanted into a main surface of a semi-insulating semiconductor substrate 1 by an ion implantation method so as to form a conductive semiconductor layer, so called an activated layer, furthermore in order to obtain an ohmic contact, ionized impurities with high density are implanted into the source electrode region 16a and drain electrode region 16b. Subsequently, the semiconductor substrate 1 is subjected to a thermal treatment and the implanted impurity ions are activated so as to obtain a desired resistance range. Subsequently, there are formed a source electrode 19a, drain electrode 19b and gate electrode 10 so as to accomplish the MESFET structure.
Generally, the high frequency characteristic of GaAs-MESFET is largely influenced by a mutual conductance g.sub.m and cut-off frequency f.sub.T. The mutual conductance g.sub.m can be increased by shortening the length of the gate or by reducing the source resistance, and the increment of the mutual conductance g.sub.m results in that the current driving ability is increased so as to operate also a large capacitive load formed by circuit conductors, a capacity between the metal wires or the like when the FET is operated in high speed. And the cut-off frequency f.sub.T can be increased by increasing the mutual conductance g.sub.m or by reducing the capacity C.sub.gs between the gate and the source, and the larger the cut-off frequency f.sub.T is, the easier the operation in high frequency becomes. That is, in order to obtain a MESFET with good high frequency characteristics, it is necessary that the length of the gate is shortened and that the source and drain regions are brought in as close to the gate electrode as possible within the range that the capacity C.sub.gs between the gate and source is not increased due to the overlap of the gate electrode and the source region. Recently, from the view point mentioned above, there is adopted a refractory gate or dummy gate so that the FET is manufactured using so called self alignment technology for positioning the source and drain regions very close to the gate electrode, thereby obtaining a high performance.
However, as the length of the gate is shortened, there occurs such a problem, so called a short channel effect, that the threshold voltage of the GaAs-MESFET is shifted toward the negative polarity, the current cut-off ability is deteriorated and that the mutual conductance g.sub.m can not be increased beyond an expected value. The short channel effect remarkably occurs especially in the self alignment type FET in which the source and drain regions are proximate to the gate electrode. According to the inventor's consideration, this is mainly because of the leak of the current which flows through the semi-insulating substrate. Because of the occurrence of the short channel effect mentioned above, the capability of GaAs-MESFET is not as improved as expected and there has been a problem that the integration with high density of the GaAs-MESFET is prevented.